Features 

• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
• Optimized for high-performance 3.3V systems
• Advanced system features
  • In-system programmable
  • Superior pin-locking and routability with Fast CONNECT™ II switch matrix
  • Extra wide 54-input Function Blocks
  • Up to 90 product-terms per macrocell with individual product-term allocation
  • Local clock inversion with three global and one product-term clocks
  • Individual output enable per output pin
  • Input hysteresis on all user and boundary-scan pin inputs
  • Bus-hold circuitry on all user pin inputs
  • Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
  • Endurance exceeding 10,000 program/erase cycles
  • 20 year data retention
  • ESD protection exceeding 2,000V

Architecture

Datasheet